【摘要】 为了给现场可编程门阵列（Field programmable gate array, FPGA）等高性能芯片提供精确、稳定且快速负载电流变化的电压源，提出了一种抗噪声、高精度及瞬态增强的低压差线性稳压器（Low-dropout regulators,LDO）电路。通过设计基于测试结果的修调电路和精确低通滤波器，为该LDO提供了高精度且抗噪声的基准电压。通过设计瞬态检测与增强电路可以快速地对负载电流的变化做出响应。通过动态的频率补偿方式，可以根据负载电流的变化动态地调整零点位置来追踪极点，保证了LDO的环路在轻载和重载下都能够保持稳定。仿真和实测结果表明，该LDO的最大负载电流为2 A，在输出电压为1.2 V典型值时，负载电流在0.5μs时间内从0.1 mA到1.6 A再回到0.1 mA进行跳变，输出电压的下冲电压和过冲电压幅值均约为0.025 V，稳定时间分别约为1.2μs和1.9μs；线性调整率约为0.003%/V，负载调整率约为0.026%/A。在抗噪声干扰方面，10 kHz时电源抑制比约为-70 dB，在10 Hz～100 kHz频率范围内积分输出噪声为4.61μVrms。更多还原

【Abstract】 In order to provide a precise, stable and rapid voltage source for high performance chips such as field programmable gate array(FPGA), an anti-noise, high-precision and transient enhanced low-dropout regulators(LDOs) circuit was proposed in this paper. A high-precision and anti-noise reference voltage was provided for the LDO by designing a tunable circuit and an accurate low-pass filter based on the test results. Transient detection and enhancement circuits were designed to quickly respond to the change of load current. By means of dynamic frequency compensation, the pole can be tracked by dynamically adjusting the zero position according to the change of load current, which ensures that the LDO loop can maintain stability under light and heavy load. The simulated and measured results show that the maximum load current of the LDO is 2 A. When the output voltage is the typical value of 1.2 V, the load current jumps from 0.1 mA to 1.6 A and back to 0.1 mA within 0.5 μs, and the amplitude of the downshoot voltage and overshoot voltage of the output voltage are all about 0.025 V, While the stabilization time are about 1.2 μs and 1.9 μs, respectively. The linear adjustment rate is about 0.003%/V, and the load adjustment rate is about 0.026%/A. In terms of anti-noise interference, the power supply rejection ratio is about-70 dB at 10 kHz, and the integrated output noise is 4.61 μVrms in the frequency range of 10 Hz to 100 kHz.更多还原