【摘要】 有序可靠位猜测随机加性噪声译码(ORBGRAND)凭借其平均时延短和通用性等优点受到广泛关注。然而，目前ORBGRAND算法和硬件实现仍然面临挑战，如最差时延长和吞吐率受限等。为了改善上述问题，该文提出将特殊的编码校验关系融入现有串行和展开架构的ORBGRAND译码器以提升硬件效率。针对串行架构，利用全局奇偶校验比特控制逻辑重量和汉明重量(HW)的迭代过程，跳过部分无效错误模式的生成与校验过程；针对展开架构，根据全局奇偶校验比特将错误模式按照HW奇偶性进行分类存储与测试。采用现有文献中的归一化方法处理后的硬件实现结果表明，所提优化的串行架构译码器吞吐率提升了80.9%，面积效率提升了48.1%；所提优化的展开架构译码器吞吐率提升了584%，面积效率提升了1 223%。更多还原

【Abstract】 Objective Ordered Reliability Bits Guessing Random Additive Noise Decoding(ORBGRAND) is a universal channel decoding algorithm characterized by its simple principles, strong decoding performance, low average latency, and hardware-friendly implementation. Since its proposal, ORBGRAND has attracted considerable attention as a promising alternative to traditional decoding methods. By combining ordered reliability bits with a noise-guessing strategy, it achieves near Maximum-Likelihood Decoding(MLD) performance while avoiding prohibitive resource overhead. However, challenges remain: its worst-case latency and limited throughput restrict practical use in high-speed communication systems. To address these gaps, this work proposes improved ORBGRAND serial and unrolled hardware architectures that incorporate a special parity-check constraint.Methods This study proposes incorporating a specific parity-check constraint into serial and unrolled ORBGRAND architectures. In the serial architecture, the global parity-check bit is used to control the iteration of Hamming Weight(HW) and Logistic Weight(LW), enabling the decoder to skip the generation and verification of invalid error patterns. In the unrolled architecture, error patterns are separately pre-stored and queried according to the global parity-check bit. This design significantly enhances the hardware efficiency of ORBGRAND decoders.Results and Discussions The improved serial and unrolled ORBGRAND decoders with the global parity-check constraint are implemented and compared with their original counterparts. Simulation results for a tested code indicate that the parity-check constraint preserves the decoding performance of conventional ORBGRAND,while reducing the average number of error pattern queries by 50% in the low to medium Signal-to-Noise Ratio(SNR) range. The architectures are synthesized using Synopsys Design Compiler with TSMC 28 nm technology.The serial ORBGRAND architecture achieves an operating frequency of 400 MHz, delivering a throughput of33.1 Gbps at SNR = 8 dB. The implementation occupies 0.18 mm2 of area, yielding an area efficiency of 183.9 Gbps/mm2. Compared with the prior art, the serial design increases throughput by 80.9% and area efficiency by48.1%. The unrolled architecture achieves a throughput of 110.6 Gbps and an area efficiency of 3.97 Gbps/mm2,corresponding to improvements of 584% in throughput and 1 223% in area efficiency relative to the prior art.Conclusions The ORBGRAND algorithm offers a promising approach for high-performance decoding in communication systems by combining high parallelism with near MLD performance. The specific parity-check constraint filters out invalid error patterns, significantly reducing the number of error pattern queries in serial and unrolled ORBGRAND architectures, without compromising performance. The serial and unrolled architectural implementations achieve notable gains in throughput and area efficiency compared with original designs. Integrating ORBGRAND with parity-check constraints thus represents a significant advancement,providing a more efficient solution for pratical communication applications. Future work will focus on further optimization of these architectures and their adaptation to diverse communication standards. In particular, the exploration of additional coding contraints may further extend the applicability of the approach.更多还原