【摘要】 SiC MOSFET和SiIGBT并联构成的混合开关（SiC/SiHyS）结构是一种优化效率和成本的综合解决方案。依靠SiC MOSFET的低导通时间构建Si IGBT的零电压开通和关断，并继承Si IGBT在高负载电流下的低导通损耗特性，从而提升系统整体效率。为了更简单高效地生成SiC/Si HyS的SiC MOSFET和Si IGBT驱动信号，该文提出一种针对最小SiC导通模式的信号调制电路，通过配置对应的RC缓冲电路中的电阻、电容值即可调节控制模式中的四个时间尺度，该方法具有灵活简单等优点。首先，理论分析最小SiC导通模式下的SiC/Si HyS结构损耗分布特性；其次，给出信号调制电路原理并介绍信号调制电路的工作原理，建立RC缓冲电路参数和时间尺度之间的函数方程；最后，基于搭建的SiC/Si HyS硬件平台，在双脉冲测试电路中验证最小SiC导通模式下的SiC/Si HyS损耗特性和所提信号调制电路的有效性，并在1.5 kW两电平逆变器中检验所提信号调制电路的动态运行特性。更多还原

【Abstract】 Silicon carbide （SiC） metal-oxide-semiconductor field effect transistors （MOSFETs） are increasingly preferred over Silicon （Si） insulated-gate bipolar transistors （IGBTs） due to their superior switching capabilities and high temperature withstand.Nonetheless,Si IGBTs maintain their position as the primary powe devices in industrial settings,attributed to their greater durability and reduced on-resistance when dealing with high currents.However,the limited switching frequency of IGBTs impedes the advancement of power electronic converters,as the lingering currents during the off-transition phase lead to elevated switching losses.A hybrid SiC/Si switch （HyS） offers a balanced solution,optimizing cost and switching performance.Typical SiC/Si HyS control methods involve deactivating Si IGBTs sooner and reactivating them after SiC MOSFETs.The minimum conduction strategy for SiC MOSFETs within the SiC/Si HyS configuration ensures that SiC MOSFETs operate exclusively during the Si IGBTs’switching intervals,which contributes to minimizing the expenses associated with SiC MOSFETs and the required chip space.Since SiC MOSFET is activated twice during the switching transients of Si IGBT,the minimum SiC MOSFET conduction mode has two more controllable time scales than the common mode of SiC/Si HyS.By dissecting each sub-stage,the loss characteristics of the minimum SiC conduction mode are quantitatively analyzed.A visual relationship regarding the time scale and load current on the conduction loss is provided in a two-level sinusoidal inverter.At low-current conditions,the output characteristic of the Si IGBT is nonlinear resulting in increased time scales that help to reduce the conduction loss.A signal modulation circuit is proposed to conveniently generate the control signal for the minimum SiC MOSFET conduction HyS.The proposed circuit comprises one OR gate （Q₄） and three D flip-flops （Q₁～Q₃）The time delay is generated by adjusting the input signal rate with the RC buffer circuit.The rising edge of s_O＿on and s_O＿off generates the driving signal for Si IGBT.The pulse of s_＿drive may be narrower than s_O＿on or s_O＿off resulting in overlapping s_O＿on and s_O＿off.Consequently,s_I fails to be pulled down by the rising edge of s_O＿off Therefore,a NAND gate Q₅ is added to reset Q₃ when an overlapping signal occurs.A simple signal modulation circuit is proposed for the minimum SiC MOSFET conduction mode of SiC/S HyS to generate the corresponding driving signals for SiC MOSFET and Si IGBT.The four-time scales of the minimum SiC MOSFET conduction mode can be flexibly adjusted by adopting the calculated values of the RC buffer circuit.The loss characteristics of the minish SiC MOSFET conduction mode of SiC/Si HyS are described quantitatively.Subsequently,the paper introduces the operation principle and functional relationship of the RC buffer circuit.The relationship between the time scale and RC values is validated using the signal modulation circuit prototype.Combined with the signal modulation circuit and a double-pulse test circuit,the effect of the time scale of the minimum SiC conduction mode on the loss distribution of the SiC/Si HyS structure is verified The proposed signal modulation circuit has good dynamic performance and stability in a 1.5 kW two-leve inverter under the unipolar frequency-doubling modulation control mode.Furthermore,the experimental result show that SiC/Si HyS achieves better efficiency and temperature-escalating performance.更多还原