节点文献
基于动态浮动逆变换比较器的10位低功耗SAR ADC
A 10-Bit Low-Power Successive-Approximation ADC with a Dynamic Comparator Based on a Floating-Inverter Amplifier
【摘要】 对于航天级CMOS图像传感器,模数转换器(ADC)是获得清晰红外图像的关键部件。针对国内航天工程的应用需求,设计低功耗、高效率的ADC是大规模CMOS图像传感器的主要指标。文章采用差分式输入结构和动态浮动逆变换前置放大比较器,设计了一种10位低功耗逐次逼近模数转换器。该ADC采用AMS 0.35μm CMOS工艺,电源电压为3.3 V,采样速率为1 MS/s。设计结果表明,所设计ADC的信噪失真比为61.02 dB,二次谐波失真为73.26 dB,有效位数达到9.84 bits,且功耗仅为260μW,版图单元面积为240μm×900μm。该设计在同等采样速率下具有更低功耗以及更优噪声表现,可应用于后续大规模CMOS图像传感器中。
【Abstract】 In aerospace engineering, analog-to-digital converter(ADC) is a crucial component used to obtain clear infrared images with complementary metal-oxide-semiconductor(CMOS) image sensors. Thus, the design of ADC devices with low power consumption and high efficiency is a primary objective to support the development of large-scale CMOS image sensors for practical applications in the domestic aerospace industry. In this study, we propose a 10-bit low-power successive-approximation ADC utilizing a differential input structure and a dynamic comparator based on a floating-inverter amplifier. The device was fabricated using the analog/mixed-signal(AMS) 0. 35-μm CMOS process and operates with a supply voltage of 3. 3 V and a sampling rate of 1 MS/s. The results of an experimental evaluation demonstrate that the proposed ADC achieved a spuriousfree dynamic range(SFDR) of 73. 26 dB, a signal-to-noise and distortion ratio(SNDR) of 61. 02 dB, and an effective number of bits(ENOB) of 9. 84 bits, while consuming only 260 μW of power. The layout unit area measures 240 μm × 900 μm. This design provides lower power consumption and superior noise performance compared to previous state-of-the-art methods at an equivalent sampling rate. Thus, our results show that the proposed ADC is suitable for applications in the development of large-scale CMOS image sensors.
【Key words】 ADC; successive approximation; floating-inverter amplifier; low-power;
- 【文献出处】 半导体光电 ,Semiconductor Optoelectronics , 编辑部邮箱 ,2025年06期
- 【分类号】TN792
- 【下载频次】46