【摘要】 基于TSMC 180 nm的1P6M标准互补金属氧化物半导体（CMOS）工艺，文章设计了一款8位分辨率的R-2R阶梯架构电压型数模转换器（DAC）。为了降低电阻失配对DAC性能的影响，该DAC采用了传输门结构开关，并通过后仿真与实际测试对其性能进行了对比分析。测试结果表明，在1.8 V电源供电下，总版图面积为820μm×820μm,DAC总功耗为91.8μW，其最大转换速率达250 M采样次数/s，微分非线性误差(D_NL)和积分非线性误差(I_NL)的最大绝对值分别为0.32 LSB和0.52 LSB。更多还原

【Abstract】 Based on TSMC 180 nm 1P6M standard complementary metal oxide semiconductor(CMOS) process, this article proposes an 8-bit resolution R-2R ladder architecture voltage-based DAC. In order to alleviate the impact of resistance mismatch on the performance of DAC, a transmission gate structure switch was adopted, and its performance was analyzed and compared through post simulation and testing. The test results show that under a 1.8V power supply, the total layout area is 820 μ m × 820 μ m, total power consumption of the DAC is 91.8 μ W, and its maximum conversion rate reaches 250 M sampling times/s. The maximum absolute values of differential nonlinear error(DNL) and integral nonlinear error(INL) are 0.32 LSB and 0.52 LSB, respectively.更多还原