【摘要】 针对飞控计算机面向多模块、多种类接口资源方向发展引发的原有飞控计算机固有性能不足、可拓展性差的问题，提出一种基于ARM+FPGA的软硬件协同工作、以PC/104作为多模块间通信总线的飞控计算机框架。该框架中针对PC/104总线与系统主存传输的带宽不匹配问题，设计了双通道数据缓冲路径，通过FPGA设计IP实现PC/104总线时序的控制，以DMA的方式实现总线与主存DDR之间的高速数据缓存。实验结果表明，所设计的飞控数据链路可实现模块间PC/104总线以40 Mb/s的速度进行数据传输，以及通过总线实现外设到系统主存之间微秒级别延迟的高速数据交换，保证了多模块工作时的数据传输效率。更多还原

【Abstract】 In allusion to the problem of insufficient inherent performance and poor scalability of the original flight control computer caused by the development of multi-module and multi-type interface resources, a flight control computer framework based on ARM + FPGA hardware and software cooperation and taking PC/104 as a multi-module communication bus is proposed.In this framework, a dual-channel data buffer path is designed to improve the bandwidth mismatch between PC/104 bus and system main memory transmission. The PC/104 bus control is realized by IP designed in FPGA, and the high-speed data cache between bus and main memory is realized by means of DMA. The experimental results show that the designed flight control computer data link can realize 40 Mb/s data transmission speed between PC/104 buse between modules, and realize high-speed data exchange with microsecond delay between peripherals and system main memory by the bus, which ensures the data transmission efficiency of multi-module operation.更多还原