【摘要】 随着超大规模集成电路的不断发展，片上供电网络的设计日益重要，需要通过计算供电网络的静态电压降来反映设计的性能。然而传统的计算方法需要耗费大量的时间，导致芯片设计周期延长。为了缩短芯片设计的周期和提高芯片设计的效率，本文提出了一个基于卷积神经网络—ResCSP-34的快速静态电压降预测模型。模型采用编码器-解码器结构，首先对残差网络ResNet34进行修改作为编码器的主体结构，然后在解码器中引入特征融合模块，并且在编码器和解码器的连接处引入注意力机制模块，最后提出了一个同时结合了均方误差、皮尔逊相关系数和平均绝对误差的损失函数对模型进行训练。实验结果表明，在CircuitNet数据集上，模型预测结果的平均绝对误差为0.7 mV,小于1 mV,皮尔逊相关系数的平均值大于0.93,接近于1,对一个片上供电网络设计进行静态电压降预测的平均总时间为7.36 s,其中卷积神经网络的平均推理时间为0.015 s。实验结果表明，ResCSP-34模型能够快速且精准地预测静态电压降。更多还原

【Abstract】 With the continuous development of VLSI circuits, the design of the on-chip power delivery network is becoming increasingly important, and the performance of the design needs to be reflected by calculating the quiescent voltage drop of the power delivery network. However, traditional computational methods are time-consuming, resulting in longer chip design cycles. In order to shorten the cycle of chip design and improve the efficiency of chip design, this paper proposes a fast static voltage drop prediction model based on convolutional neural network—ResCSP-34. The model adopts the encoder-decoder structure, firstly the residual network ResNet34 is modified as the main structure of the encoder, then the feature fusion module is introduced into the decoder, and the attention mechanism module is introduced at the connection of the encoder and the decoder, and finally a loss function combining the mean square error, Pearson correlation coefficient and mean absolute error is proposed to train the model. Experimental results show that on the CircuitNet dataset, the average absolute error of the model prediction results is 0.7 mV, which is less than 1 mV, the average value of the Pearson correlation coefficient is greater than 0.93, close to 1, and the average total time for static voltage drop prediction for an on-chip power supply network design is 7.36 s, and the average inference time of the convolutional neural network is 0.015 s. Experimental results show that the ResCSP-34 model can quickly and accurately predict the quiescent voltage drop.更多还原