【摘要】 万物感知、万物互连和万物智能推动集成电路进入新一轮的高速发展期并促进对高性能芯片需求的指数级增长。后摩尔时代，芯片性能的进一步提升面临大面积芯片良率降低、功耗控制难、片内互连密度大以及制造成本高等难题。因此业界开始将原来多功能、高集成度的复杂So C芯片分割做成单独的芯粒（Chiplet），再通过先进封装工艺集成为集成芯片或微系统产品。对芯粒集成技术特征及模式、发展历史、优缺点进行了梳理与阐述，同时归纳总结了芯粒集成的关键技术挑战，并对未来发展进行了展望。更多还原

【Abstract】 Perception, interconnection, and intelligence of all things are driving integrated circuits into a new phase of rapid development and fostering exponential growth in the demand for high-performance chips. In the post-Moore era, further improvement in chip performance faces challenges such as yield rate reduction for large-area chips, difficult power consumption control, high interconnect density within the chip, and high manufacturing costs. Therefore, the industry has begun to divide previously multifunctional, highly integrated complex system on chip(So C) into individual Chiplets, and then integrate them into chips or microsystem products through advanced packaging technologies. The characteristics and modes, development history,advantages and disadvantages of Chiplet integration technology are reviewed and elucidated, the key technical challenges of Chiplet integration are summarized, and an outlook on future development is provided.更多还原