【摘要】 基于Itoh-Tsujii algorithm（ITA）算法，提出了一种具有级联模平方模块的新型低延迟架构，并推导出了该架构的时钟周期延迟，级联模平方模块的复杂度可以通过矩阵重量进行评估.采用可移动的内部流水线层级来优化关键路径.使用Virtex-7 FPGA平台进行实验，分别给出了对于GF(2¹⁶³)、GF(2²⁸³)和GF(2⁵⁷¹)三个二进制域上的最优模平方模块（optimal exponentiation blocks,OEBs）.此外，为了便于比较，在Virtex-4 FPGA平台进行了测试，并与现有研究成果进行了对比.结果显示，基于OEBs的架构性能具有显著的提升，本文架构在3个域中的延迟相较于现有研究分别至少具有9.09%,10.81%以及428.95%的提升.更多还原

【Abstract】 Multiplicative inverse operations on binary fields are widely used in cryptographic algorithms.The Itoh-Tsujii algorithm （ITA） enables multiplicative inverse operations by modulo multiplication and modulo squaring in a particular order.In this paper,a low-latency novel architecture with cascaded modulo-square modules was proposed based on the ITA algorithm and the clock cycle delay of the architecture was derived,evaluating the complexity of the cascaded modulo-square modules based on matrix weights.And then,the critical path from cascaded modulo-square modules to multiplier was optimized based on a movable internal pipeline hierarchy.Finally,experiments were carried out based on the Virtex-7 FPGA platform,which gives the Optimal Exponentiation Blocks （OEBs） for the three binary domains GF(2¹⁶³),GF(2²⁸³) and GF(2⁵⁷¹),respectively.In addition,to be fair,tests were performed on Virtex-4 FPGA platform and compared with the existing research results The results show that the performance of the OEBs-based architecture can been improved significantly,and the latency of the proposed architecture in the three fields possesses at least 9.09%,10.81%,and 428.95%improvement compared with the existing studies,respectively.更多还原