【摘要】 针对嵌入式设备对以太网接入的需求，提出一种基于FPGA的千兆以太网MAC控制器的硬件架构。通过FPGA编程实现IEEE 802.3规定的数据封装和介质访问控制等功能。设计了一种具备帧清除和重读功能的改进型异步FIFO,用于存储帧数据，既解决跨时钟域数据的同步问题，又方便进行发送时帧的重发和发送或接收时错误帧的丢弃。经过Modelsim仿真和FPGA硬件测试，MAC控制器的功能得到验证，且仅使用少量的逻辑资源。更多还原

【Abstract】 Aiming at the requirement of embedded devices for Ethernet access, a hardware architecture of gigabit Ethernet MAC controller based on FPGA was proposed.The functions of data encapsulation and media access control specified in IEEE 802.3 were realized by FPGA programming.An improved asynchronous FIFO with frame clearing and rereading functions was designed to store frame data, which not only solved the problem of data synchronization across clock domains, but also facilitated retransmission of frames during transmission and discarding of erroneous frames during transmission or reception.After Modelsim simulation and FPGA hardware test, the function of MAC controller is verified, and only a small amount of logic resources are used.更多还原