【摘要】 在SerDes电路中，高速数据传输的关键在于均衡的速率，因此随着SerDes对数据传输速率要求越来越高，对SerDes中接收器的判决反馈均衡器的速率要求也在提高。作为自适应判决反馈均衡器的关键组成部分，比较器的延时大小决定了自适应均衡器的判决容限。为了满足低压应用对高速率比较器的低延迟要求，文章基于传统双尾比较器提出一种新的适用于SerDes接收器中判决反馈均衡器的高速差分信号动态比较器电路。在TSMC 28 nm CMOS工艺下，当电源电压为1 V时，平均延迟时间为52.58 ps,可满足高达15 Gbit/s数据速率的判决反馈均衡器应用需求。更多还原

【Abstract】 In the SerDes circuits, the key of high speed data transmission is the equalized rate, so as the rate of data transmission increased, the rate of the decision feedback equalizer in the receiver of SerDes are also increasing. As a key component of adaptive decision feedback equalizer, delay time of the comparator determines the rate tolerance of the adaptive decision feedback equalizer. In order to meet requirement of low voltage for high speed comparator, this paper proposed a new comparator circuit which is suitable for high speed decision feedback equalizer. Based on a traditional two-tail comparator, this new comparator circuit was designed in TSMC 28 nm CMOS process. When the supply voltage is 1 V, the average delay time is 52.58 ps. It can meet the requirements of the decision feedback equalizer which data rate is up to 15 Gbit/s.更多还原