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一种高压精密低输入偏置电流JFET型放大器

A High Voltage Precision Low Input Bias Current JFET Amplifier

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【作者】 张键胡辉勇周远杰何峥嵘

【Author】 ZHANG Jian;HU Huiyong;ZHOU Yuanjie;HE Zhengrong;Xidian University;The 24th Research Institute of China Electronics Technology Group Corporation;

【通讯作者】 胡辉勇;

【机构】 西安电子科技大学中国电子科技集团公司第二十四研究所

【摘要】 基于40 V高压互补双极性结型晶体管(BJT)兼容结型场效应晶体管(JFET)工艺,设计了一种高压精密低输入偏置电流JFET型放大器,介绍了放大器总体架构以及工作原理。电路内部采用JFET输入器件降低输入偏置电流,提高带宽,用修调电阻降低输入失调电压;采用四核跨导结构优化中间级提高运放的压摆率;输出级采用互补推挽输出结构防止交越失真,同时提高功率驱动能力;偏置电路利用JFET作恒流源,保证在不同工作电压下稳定供电。芯片流片测试结果表明,该放大器在±5~±13 V工作电压条件下,输入失调电压≤80μV;输入偏置电流≤1.5 pA;开环增益≥107 dB;增益带宽积≥25 MHz;压摆率≥50 V/μs。

【Abstract】 Based on the 40 V high voltage complementary bipolar junction transistor(BJT) compatible with junction field effect transistor(JFET) technology, a high voltage precision low input bias current JFET amplifier was designed. The overall structure and working principle of the amplifier were described. Inside the circuit, JFET input devices were used to reduce the input bias current and improve the bandwidth. The input offset voltage was reduced by adjusting the resistance. The fourcore transconductance structure was used to optimize the intermediate stage to improve the swing rate of the op amp. The complementary push-pull output structure was used in the output stage to prevent crossover distortion and improve the power driving ability. The bias circuit used JFET as a constant current source to ensure stable power supply under different working voltages. The chip test results show that, under ±5-±13 V power supply conditions, the circuit has the input offset voltage ≤80μV; the input bias current ≤1.5 pA; the large signal voltage gain ≥107 dB; the gain bandwidth product ≥25 MHz; the slew rate ≥50 V/μs.

  • 【文献出处】 固体电子学研究与进展 ,Research & Progress of SSE , 编辑部邮箱 ,2023年06期
  • 【分类号】TN722;TN386
  • 【下载频次】24
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