【摘要】 本研究针对谐振时钟网络在集成电路设计中的数字化实现,提出了一种全局时钟功耗优化(MRC)方法,简化了谐振时钟网络在数字化设计中的集成过程。当前,依赖传统仿真工具构建谐振网络的仿真周期较长,且现有谐振电路模型无法满足快速设计与数字化建库要求。本文根据谐振电路三段式电路状态提出一种折线化模型降阶方法,可快速实现对当前各类谐振电路波形的准确刻画;本文同时基于此模型给出全局功耗优化目标函数,为电路选型提供指导。与12 nm Fin-FET工艺下实际电路的Spice后仿结果进行比较,本文模型精确度在90%以上,可以准确模拟实际功耗变化趋势,基于Matlab实现的优化方案相比Spice仿真提速10~5倍。更多还原

【Abstract】 Aiming at the digital implementation of resonant clock network in the integrated circuit design,this paper proposes a modeling and optimization method of resonant clock circuits (MRC),which simplifies the integration process of resonant clock networks.At present,traditional simulation tools for building resonant circuit models is time consuming,and the existing resonant circuit models cannot meet the requirements of rapid implementation and digital library construction.According to the three-stage circuit state of the resonant designs,the polyline reduction model in this paper can obtain the current waveforms of various resonant circuits quickly and accurately.An optimization objective function of global power consumption is also given based on this model,providing a theoretical basis for the selection of circuit parameters.The post-Spice simulation results based on 12 nm Fin-FET technology show that the model accuracy is more than 90%and can accurately fit the actual power consumption trend.Matlab-based implementation of the proposed model can achieve 10~5times speedup compared with Spice-based simulation.更多还原