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波动动态差分逻辑RISC-V CPU芯核的功耗抑制技术研究
The Power Suppression Techniques for the DPA-resistant RISC-V CPU Core Based on WDDL
【摘要】 差分功耗分析(DPA)攻击不仅威胁加密硬件,对加密软件的安全性也构成严重挑战。将波动动态差分逻辑(WDDL)技术应用在RISC-V指令集的处理器芯核上可减少功耗信息的泄露。但是,WDDL技术会给电路引入巨大的功耗开销。该文针对基于WDDL的RISC-V处理器芯核提出两种功耗抑制方法。虽然随机预充电使能技术与指令无关,而预充电使能指令技术需要扩充指令集,但这两种方法都是属于轻量级的设计改进。仿真结果表明,采用了随机预充电使能技术和预充电使能指令技术的Rocket芯核的电路功耗分别是原始的WDDL Rocekt芯核功耗的42%和36.4%。
【Abstract】 Differential Power Analysis(DPA) is a serious threat to cryptographic hardware and software. The RISC-V processor core based on Wave Dynamic Differential Logic(WDDL) is implemented to mitigate the power leakage. However, the WDDL technique results in a dramatic increase in circuit power. For WDDLbased RISC-V CPU cores, two power suppression techniques are proposed in the paper. Both of them are lightweight solutions. The simulation results show that the circuit power of the DPA-resistant Rocket core with the random precharge enabling technique and the precharge enabling instruction technique can be reduced to 42% and 36.4% of that of the original WDDL based counterpart, respectively.
【Key words】 Differential Power Analysis(DPA); RISC-V core; Wava Dynamic Differential Logic(WDDL); Power leakage; Power suppression;
- 【文献出处】 电子与信息学报 ,Journal of Electronics & Information Technology , 编辑部邮箱 ,2023年09期
- 【分类号】TP332
- 【下载频次】4