【摘要】 为提升衰减精度和附加相移性能，采用电容补偿技术吸收了开关管的寄生效应，设计了2款5位毫米波反射式衰减器芯片.通过剖析3种基本电容补偿拓扑，借助史密斯圆图，分析负载反射系数、衰减量和附加相移随补偿电容的变化情况，总结出采用电容补偿技术设计反射式衰减器的设计流程和优化方法，并流片验证.2款芯片均集成有1个五位衰减器和1个单刀双掷开关，总芯片面积均为3 mm×1 mm.其中芯片A基于0.5μm砷化镓PHEMT工艺，采用了尾电容补偿技术；芯片B基于0.15μm砷化镓PHEMT工艺，采用了开关管前/后电容补偿技术.结果表明，2款芯片包含开关的插入损耗均小于4.5 dB,其中衰减器的插入损耗均小于3 dB,衰减均方根误差都小于0.4 dB,输入1 dB压缩功率都大于25 dBm,芯片A衰减相位变动小于±5°,芯片B衰减相位变动小于±2.5°.更多还原

【Abstract】 To improve the attenuation accuracy and phase variation performance, two 5-bit millimeter-wave reflective attenuators with a capacitive compensation technique in gallium arsenide(GaAs) pseudomorphic high-electron-mobility transistor(PHEMT) process are presented. The parasitic effect of a millimeter-wave switch can be absorbed effectively in the design of the reflection load with capacitive compensation. Thus, attenuation and phase accuracy can be improved. Three basic capacitive compensation topologies were presented, and based on the analysis of the reflection coefficient on the Smith chart, the corresponding attenuation and phase variation were given. Furthermore, the design flow and optimization method of the reflective attenuator based on the capacitive compensation technique were summarized. Both chips are integrated with a 5-bit attenuator and a single-pole double-throw(SPDT) switch, and the chip size is 3 mm × 1 mm. Chip A with tail capacitance compensation was fabricated by a 0.5 μm GaAs PHEMT process, and Chip B with the compensation of the shunt capacitors before and after the switch was fabricated by a 0.15 μm GaAs PHEMT process. For both chips, the insertion loss(IL) with the SPDT switch is less than 4.5 dB, the IL of the 5-bit attenuator is less than 3 dB, the root-mean-square attenuation error is less than 0.4 dB, and the input 1 dB gain compression power is greater than 25 dBm. The phase variations of Chips A and B are less than ±5°and ±2.5°, respectively.更多还原