【摘要】 高性能的半导体功率器件依赖于金属/半导体、半导体/半导体或者半导体/绝缘体间的高质量界面的形成.本文报道了三种提取β-氧化镓（β-Ga₂O₃）基器件界面陷阱密度(Interface Trap Density, D_it)的方法,分别用于肖特基势垒二极管（SBD）、PN异质二极管和金属/氧化物/半导体电容（MOS Capacitor）.利用对应频率下的电容-电压和电导-电压特性获得了Ni-SBD金半界面的陷阱密度.本文还引入了导纳谱（Admittance Spectroscopy, AS）分析NiO/β-Ga₂O₃PN二极管的界面陷阱密度.精确的高-低频电容法则用于MOS Capacitor的D_it测量.本文验证的界面态测量与提取方法为氧化镓器件界面处理提供量化手段,同时为获得高性能氧化镓器件指明方向.更多还原

【Abstract】 High performance devices need a high quality interface between metal/semiconductor, semiconductor/semiconductor or semiconductor/insulator. In this work, we report three different methods to obtain the interface trap density(D_it) in β-Ga₂O₃-based SBD, PN, and MOS capacitors. The characteristics of capacitance-voltage and conductance-voltage corresponding to frequency demonstrate a low Ditfor Ni-SBD. Also, we introduce admittance spectroscopy（AS） to evaluate Ditof NiO/β-Ga₂O₃ PN diode. Moreover, the accurate high-low frequency capacitance method has been adopted for the MOS capacitor. The verified methods for extracting D_it Boffer a quantification of the quality of interface, which contribute to interface processing and device design.更多还原