【摘要】 基于系统级封装(System in Package, Si P)技术,结合自研自主可控DSP处理器"魂芯"II-A和多片DDR3颗粒,详细介绍了一款高速动态存储控制一体化Si P设备的设计方案和仿真验证分析结果。重点介绍了此款Si P的电路拓扑设计、版图设计,并从拓扑结构波形仿真、DDR3时序裕量计算、与板级实现方案对比三方面对其PCB后仿进行了分析和验证,仿真结果符合规范要求,证明了所采用的Fly-By拓扑适用于CPU与多片DDR3颗粒所组成的一体化Si P设备,且Si P设备性能优于板级实现方案。更多还原

【Abstract】 Based on the system in package(Si P) technology, combined with a self-developed independent controllable DSP processor( "HX" II-A) and multi-chip DDR3 particles, the design scheme and simulation verification analysis of a high-speed dynamic memory control integrated Si P is introduced in detail. Focused on the circuit topology design and the layout design of this Si P, its PCB post-simulation is verified from three aspects, including topology simulation waveform, DDR3 timing margin calculation, and comparison with board-level implementation schemes. The simulation results are compounded and standardized, and the requirements prove that the adopted Fly-By topology is suitable for integrated Si P equipment which is composed of CPU and multiple DDR3 particles. In addition, the performance of Si P equipment is better than the board-level implementation scheme.更多还原