【摘要】 针对嵌入式系统处理器代码量指数式增长带来的设计与验证难题,提出一种适用于RISC-V指令集架构处理器的Bitmask代码压缩技术.结合RISC-V指令集特点,设计了混合编码与分离字典相结合的Bitmask代码压缩算法;在不影响处理器结构和Cache工作机制的基础上,设计精简的硬件解压缩单元,减小了嵌入式系统处理器所需的程序内存空间.采用面向RISC-V指令集的混合编码压缩指令格式,减小原始指令码的码字长度,改善了代码压缩率;采用分离的两个字典结构,在不影响代码压缩率的前提下,减小了硬件解压缩延迟.结果表明,在RISC-V指令集架构上不增加过多硬件开销的情况下,代码压缩率平均为61.1%,大大减小了处理器所需的程序内存空间.更多还原

【Abstract】 Aiming at design and verification problems caused by the exponential growth of the code size in the embedded system processors, the Bitmask-based code compression technology for processors based on RISC-V instruction set architecture is presented. Based on the features of RISC-V instruction set, a Bitmask-based code compression algorithm combined with mixed encoding and separate dictionary is designed. Without affecting the processor structure and Cache working mechanism, a simple and efficient hardware decompression unit is designed to reduce the program memory space required by the embedded system processor. Mixed encoding format for RISC-V instruction set is used to reduce the length of the original instruction, which improves the code compression rate. Besides, two separated dictionaries are used to obtain a small hardware decompression delay without affecting the code compression rate. The experimental results show that the code compression ratio is 61.1% on average without much hardware overhead on the RISC-V instruction set architecture, which greatly reduces the program memory space required by the processor.更多还原