节点文献
AES加密算法的改进及FPGA实现
Research on Improved AES Encryption Algorithm Based on FPGA
【摘要】 为提高数据传输的保密性和加密解密的高效性,利用数字信封技术,对传统的AES加密算法进行了改进.将AES加密算法和非对称加密中的RSA加密算法相结合,利用RSA加密算法中陷门单向置换变换的特点,对敏感密钥信息key单独进行加密;最后,基于FPGA予以实现.实验验证结果表明,改进程序完成了数据加解密算法,可实现错误率为零,加解密速度达到1.62 Mb/s,比文献[2]研究结果提高了近25.56%,达到了预期效果.
【Abstract】 In order to improve the confidentiality of data transmission and the efficiency of encryption and decryption,the traditional AES encryption algorithm is improved by using digital envelope technology.The AES encryption algorithm is combined with the RSA encryption algorithm in asymmetric encryption.The sensitive key information key is encrypted separately by using the feature of one-way permutation transformation of trap door in RSA encryption algorithm.Finally,it is implemented based on FPGA.The experimental verification results show that the data encryption and decryption algorithm is completed through the improved program,which can achieve zero error rate and 1.62 Mb/s encryption and decryption speed.It is nearly 25.56% higher than the research results in literature [2] which had achieved the expected effect.
【Key words】 AES encryption; RSA encryption; FPGA; digital envelope technology;
- 【文献出处】 兰州交通大学学报 ,Journal of Lanzhou Jiaotong University , 编辑部邮箱 ,2020年03期
- 【分类号】TP309.7;TN791
- 【被引频次】14
- 【下载频次】733