【摘要】 本文设计了一种能够产生256路采样时钟、低抖动的多相延迟锁相环电路。该电路由鉴频鉴相器、电荷泵、环路滤波器和压控延时链四部分组成,现采用上海华虹宏力半导体制造有限公司130 nm CMOS工艺,完成了电路设计与仿真;仿真结果表明在典型1 ns相位延迟下,输出时钟相位延迟均值为0.999 ns,相位延迟抖动为18.61ps,可应用于给开关电容阵列提供稳定的采样时钟。更多还原

【Abstract】 In this paper, a multi-phase delay phase-locked loop circuit capable of generating 256 sampling clocks and low jitter is designed. The circuit consists of a phase frequency detector, a charge pump, a loop filter, and a voltage-controlled delay line. Now it uses Shanghai Huahong Grace Semiconductor Manufacturing Co., Ltd. 130 nm CMOS process to complete the circuit design and simulation; The simulation results shows that under a typical 1 ns phase delay, the average phase delay of the output clock is 0.999 ns, and the phase delay jitter is 18.61 ps, which can be used to provide a stable sampling clock for the switched capacitor array.更多还原