【摘要】 处理器访存性能对其整体性能有着很大的影响,访存子系统的设计显得尤为重要。高性能超标量处理器的访存子系统中存在多个关键队列,如何快速进行设计折中,成为设计的关键。本文采用软件模拟器和回归模型结合的建模方法,提出了一个面向访存子系统关键队列的回归分析模型,并设计实现了相应的访存子系统模拟器。将软件模拟器与目标处理器设计的现场可编程门阵列(FPGA)原型验证平台进行准确性校准,并采用回归模型对软件模拟器的模拟数据进行分析,结果表明:实验验证结果稳定且对于所测试程序误差在10%以内。该建模方法可以量化分析访存子系统中关键队列大小与性能之间的关系,有效扩大硬件设计空间探索的范围,加快高性能处理器访存子系统的优化设计。更多还原

【Abstract】 Memory access performance of processors has a great impact on the overall performance, so the design of memory subsystem is particularly important. There are many key queues in the memory subsystem of high performance superscalar processors. How to quickly get the trade-off of design becomes the key for design. This paper uses a way that combines software simulator with regression model. It proposes a regression analysis model for key queues of memory subsystem whose corresponding simulator is designed and implemented. By calibrating the accuracy of the software simulator with the target processor’s FPGA prototype verification platform and using the regression model to analyze the simulation data of the simulator, the results show that the experimental verification results are stable and the error of the tested program is less than 10%. This modeling method can quantitatively analyze the relationship between key queue size and performance in memory subsystem, effectively expand the scope of hardware design space exploration, and accelerate the optimization design of memory subsystem for high performance processors.更多还原