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Charge trapping memory device based on the Ga2O3 films as trapping and blocking layer

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【作者】 白冰； 王宏； 李岩； 郝云霞； 张博； 王博平； 王子航； 杨红旗； 高启航； 吕超； 张庆顺； 闫小兵；

【Author】 Bing Bai;Hong Wang;Yan Li;Yunxia Hao;Bo Zhang;Boping Wang;Zihang Wang;Hongqi Yang;Qihang Gao;Chao Lü;Qingshun Zhang;Xiaobing Yan;Key Laboratory of Optoelectronic Information Materials of Hebei Province, Key Laboratory of Digital Medical Engineering of Hebei Province, College of Electron and Information Engineering, Hebei University;Department of Electrical and Computer Engineering, Southern Illinois University Carbondale;Department of Materials Science and Engineering, National University of Singapore;

【通讯作者】 张庆顺;闫小兵;

【机构】 Key Laboratory of Optoelectronic Information Materials of Hebei Province, Key Laboratory of Digital Medical Engineering of Hebei Province, College of Electron and Information Engineering, Hebei University； Department of Electrical and Computer Engineering, Southern Illinois University Carbondale； Department of Materials Science and Engineering, National University of Singapore；

【摘要】 We present a new charge trapping memory（CTM） device with the Au/Ga2O3/SiO2/Si structure, which is fabricated by using the magnetron sputtering, high-temperature annealing, and vacuum evaporation techniques. Transmission electron microscopy diagrams show that the thickness of the SiO2 tunneling layer can be controlled by the annealing temperature.When the devices are annealed at 760℃, the measured C–V hysteresis curves exhibit a maximum 6 V memory window under a ±13 V sweeping voltage. In addition, a slight degradation of the device voltage and capacitance indicates the robust retention properties of flat-band voltage and high/low state capacitance. These distinctive advantages are attributed to oxygen vacancies and inter-diffusion layers, which play a critical role in the charge trapping process.

【Abstract】 We present a new charge trapping memory（CTM） device with the Au/Ga2O3/SiO2/Si structure, which is fabricated by using the magnetron sputtering, high-temperature annealing, and vacuum evaporation techniques. Transmission electron microscopy diagrams show that the thickness of the SiO2 tunneling layer can be controlled by the annealing temperature.When the devices are annealed at 760℃, the measured C–V hysteresis curves exhibit a maximum 6 V memory window under a ±13 V sweeping voltage. In addition, a slight degradation of the device voltage and capacitance indicates the robust retention properties of flat-band voltage and high/low state capacitance. These distinctive advantages are attributed to oxygen vacancies and inter-diffusion layers, which play a critical role in the charge trapping process.

【关键词】 charge trapping memory； SiO2 tunneling layer； annealing temperature；
【Key words】 charge trapping memory； SiO2 tunneling layer； annealing temperature；
【基金】 Project supported by the National Natural Science Foundation of China(Grant Nos.61674050 and 61874158);the Top-notch Youth Project in Hebei Province,China(Grant No.BJ2014008);the Outstanding Youth Project of Hebei Province,China(Grant No.F2016201220);the Outstanding Youth Cultivation Project of Hebei University,China(Grant No.2015JQY01);the Project of Science and Technology Activities for Overseas Researcher,China(Grant No.CL201602);the Institute of Baoding Nanyang Research-New Material Technology Platform,China(Grant No.17H03);the Project of Distinguished Young of Hebei Province,China(Grant No.A2018201231);the Training Program of Innovation and Entrepreneurship for Undergraduates,China(Grant Nos.201710075013and 2017075);the Support Program for the Top Young Talents of Hebei Province,China(Grant No.70280011807);Training and Introduction of Highlevel Innovative Talents of Hebei University,China(Grant No.801260201300);Hundred Persons Plan of Hebei Province,China(Grant Nos.606999919001,606999919013,606999919014,and 801260201300);Innovation Funding Project of Hebei Province,China(Grant No.CXZZBS2019030)
  • 【文献出处】 Chinese Physics B ,中国物理B , 编辑部邮箱 ,2019年10期
  • 【分类号】TP333
  • 【下载频次】25
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