【摘要】 采用VHDL语言设计适用于硬件化的实时操作系统调度器,基于FPGA使用组合电路和时序电路完成了系统内核调度器的搭建。该调度器在Variable Multi-Processing (VMP)运行模式下,可在一个系统时钟之内完成多核处理器的任务调度,并可同时管理不同芯片系统,完成异构处理器系统的统一调度。由于该调度器是采用门电路搭建而成的,存在于芯片系统之外,因此具有极高的稳定性和系统性能,并且可以根据需要进行裁剪。更多还原

【Abstract】 The Very-high-speed integrated circuit Hardware Description Language (VHDL) is used to complete the hardware design of a real-time operating system scheduler,and the system core scheduler is built using the combination circuits and sequential circuits based on the Field Programmable Gate Array (FPGA). Under the Variable Multi-Processing (VMP) operation mode proposed in the paper,the scheduler can complete the task scheduling of multi-core processors within one system clock,and can manage different chip systems at the same time to complete the unified scheduling of heterogeneous processor systems. Because the scheduler is built with the gate circuits,it exists outside of the chip system,has the characteristics of high stability and system performance,and is scalable.更多还原