节点文献
0.35μm高速真随机数芯片设计
Design of an ASIC TRNG Using 0.35 μm CMOS Technology
【摘要】 设计了一种基于混合布尔网络的混沌真随机数发生器,其熵源由18节点自治布尔网络构成,用于产生高幅值(~3 V)、大带宽(~780 MHz)的布尔混沌;利用同步布尔网络对布尔混沌进行采样、量化,最终实现了实时速率为100 Mbps的真随机数产生。同时完成了真随机数发生器的ASIC芯片设计,芯片采用中芯国际SMIC 0.35μm 3.3 V CMOS标准工艺,核心电路面积0.02 mm~2.利用Cadence Spectre仿真器,对芯片版图进行了后端仿真验证。仿真结果表明,该芯片可以在100 MHz时钟下输出满足随机性检测标准的真随机数序列。
【Abstract】 A chaotic true random number generator based on hybrid Boolean network was proposed. The entropy source is composed of an 18-node autonomous Boolean network, which is used to generate Boolean chaotic with high amplitude(~3 V) and large bandwidth(~780 MHz). The Boolean chaos is sampled and quantized by using a synchronous Boolean network, and finally a real random number with a real-time rate of 100 Mbps is generated. At the same time, the ASIC chip design of the true random data generator was completed. The chip adopts SMIC 0.35-μm 3.3 V CMOS standard process, and the core circuit area is 0.02 mm~2. Back-end simulation verification of the chip layout was performed using the Cadence Spectre simulator. The simulation results show that the chip can output a sequence of true random numbers satisfying the randomness detection standard at 100 MHz clock.
【Key words】 ASIC; boolean chaos; random number generator; random test; autonomous boolean network;
- 【文献出处】 太原理工大学学报 ,Journal of Taiyuan University of Technology , 编辑部邮箱 ,2019年06期
- 【分类号】TN402
- 【下载频次】129