节点文献
基于异构FPGA的卷积网络加速器
Heterogeneous FPGA Based Convolutional Network Accelerator
【摘要】 基于神经网络的方法计算量通常十分庞大,限制方法在嵌入式场景领域的应用.为了解决这一问题,文中提出基于异构现场可编程门阵列的卷积网络加速器.采用滑动窗并行加速卷积计算过程,可同时处理不同输入、输出通道的卷积过程.同时结合网络量化过程进行8 bit定点加速器设计,降低计算资源的使用.实验表明,文中定点加速器运算速度较快,功耗较小,算法性能损失较小.
【Abstract】 Computational complexity of neural network methods is high, and its application in embedded scenarios is limited. To solve this problem, a convolutional network accelerator based on heterogeneous field programmable gate array is proposed. The sliding window is employed to accelerate the convolution calculation process, and thus the convolution process of different input and output channels can be handled. A 8 bit fixed-point accelerator is designed combining network quantization process, and the usage of computing resources is reduced. Experiments demonstrate that the proposed fixed-point accelerator achieves a higher computing speed and a lower power consumption with a less performance loss.
【Key words】 Convolutional Neural Network; Field Programmable Gate Array(FPGA); Accelerator; Parallelism; Fixed-Point;
- 【文献出处】 模式识别与人工智能 ,Pattern Recognition and Artificial Intelligence , 编辑部邮箱 ,2019年10期
- 【分类号】TP183;TN791
- 【被引频次】6
- 【下载频次】252