【摘要】 提出了一种带n型浮空埋层的超低比导通电阻的变k槽型LDMOS（TLDMOS）。新结构在漂移区内引入变介电常数（VK）的深槽结构和自驱动的U型p区,不仅可提高漂移区的掺杂浓度,还可优化体内电场分布。衬底中引入的n埋层在器件阻断时进一步调制漂移区的电场分布。同时,额外p衬底/n埋层结的引入提高了LDMOS的纵向耐压。导通时,由于集成低压电源施加于U型p区,在其周围产生的电子积累层使器件在不增加栅电荷的情况下显著降低了比导通电阻(R_on,sp)。仿真结果表明,与传统TLDMOS相比,在相同元胞尺寸下,新结构的击穿电压提高了59.3%,R_on,sp降低了86.3%。更多还原

【Abstract】 An ultra-low specific on-resistance trench LDMOS（TLDMOS）with an n-type floating buried layer was proposed.A variable-kdielectric trench and a self-driven U-type p region were introduced in the drift region of the proposed structure,which not only increased the doping concentration of the drift region,but also optimized the electric field distribution in the drift region.The n-type buried layer in the substrate could further modulate the electric field distribution in the N-drift region under both the source and drain sides.A higher vertical V_B of the LDMOS attributed to the additional vertical PN junction introduced by the n-type buried layer.During the on-state,a low voltage supply was applied to the U-type p-region,and the electrons that were accumulated along the U-type p-region contributed to the low resistance without increasing the gate charge.Simulation results indicated that the V_B of the proposed TLDMOS increased by 59.3% and the R_on,sp decreased by 86.3% compared with that of the conventional TLDMOS with the same cell pitch.更多还原