【摘要】 提出了一种具有可变相位累加器电路结构的新型全数字锁相环。采用EDA技术完成了对该系统的设计,利用ModelSim软件对所设计的电路进行了系统仿真实验,并进行了硬件实验验证。实验结果表明,含有可变相位累加器构成的全数字锁相环可拓展系统环路的锁相范围,提高锁相频率,降低系统总功耗,并且不会增加FPGA芯片内部的逻辑资源。由于该锁相环内部信号的传递是并行传输,故可大大提高系统的锁相速度。该锁相环能够作为功能模块嵌入进电子系统芯片中,可广泛应用于通信、电子测量和自动控制等领域。更多还原

【Abstract】 This paper presents a novel all-digital phase-locked loop with variable phase accumulator circuit structure. The design of the system is completed by using EDA technology, and the system simulation experiment is carried out by using ModelSim soft-ware, and the hardware experiment is carried out. The experimental results show that the all-digital PLL with variable phase accu-mulator can extend the phase-locked range of the system loop, increase the frequency of PLL, reduce the total power consumption of the system, and do not increase the logic resources in the FPGA chip. Because the internal signal of the PLL is transmitted in parallel, the speed of PLL can be greatly improved. The PLL can be embedded into an electronic system chip as a functional mod-ule, and can be widely used in communication, electronic measurement and automatic control.更多还原