【摘要】 针对绝缘体上硅(SOI)NMOS侧壁晶体管的电流特性研究,利用Verilog-A语言建立了一个含有漏致势垒降低(DIBL)效应的侧壁晶体管电流模型。进一步基于SOI NMOS总剂量辐射效应机理将总剂量辐射效应引入该模型。新建立的侧壁晶体管电流模型既保留了侧壁晶体管本身的电流特性,又可以反映总剂量辐射导致的电流变化。将新的侧壁晶体管总剂量模型嵌入商用SOI模型仿真验证的结果表明,该SOI侧壁晶体管总剂量模型在不同漏端偏置电压下的仿真与测试结果高度吻合,可以给电路设计者提供可靠的仿真结果,缩短抗辐射电路开发周期。更多还原

【Abstract】 According to a detail discussion on I-Vcharacteristics of the sidewall transistor in SOI NMOS,a model includes drain induced barrier lowing(DIBL)effect for the sidewall transistor was established with Verilog-A.Further,total ionizing dose(TID)effect was embedded into the model on the basis of TID mechanism.The I-V model for the sidewall transistor TID effect reflects not only the I-Vcharacteristics of the sidewall transistor,but also that of the TID effect.Embedding the presented model into the commercial SOI model,it is shown that the simulation result is in good agreement with the TID experiment data under different drain bias.This model can provide more reliable simulation results for circuit designer,shortening the development cycle of radiation hardened circuit.更多还原