【摘要】 基于TSMC90nm CMOS工艺设计了一款高速锁相环.为优化锁相环整体的相位噪声及参考杂散性能,分析了差分电荷泵和LC压控振荡器的相位噪声,并且讨论了多模分频器的设计方法.高速锁相环的整体芯片版图面积为490μm×990μm.测试结果表明,在频偏1MHz处的相位噪声为-90dBc,参考杂散为-56.797dBc.更多还原

【Abstract】 A high speed phase locked loop(PLL)was designed based on TSMC 90 nm CMOS process.In order to optimize phase noise and reference spur,the main modules of PLL such as charge pump and LC voltage controlled oscillator(VCO)were analyzed and improved.The design method of multi-modulus divider(MMD)was studied in detail.The layout of the high speed PLL was optimized and whole chip area was arranged in 490μm×990μm.The testing results show that,the in-band phase noise can reach -90 dBc at 1 MHz frequency offset and the reference spur is -56.797 dBc.更多还原