节点文献
一种高性能HEVC整像素运动估计硬件设计
A High Performance Hardware Design for HEVC Integral Motion Estimation
【摘要】 针对整像素运动估计提出了一种适合硬件实现的运动估计算法,并设计了硬件架构.通过在不同划分深度的编码单元中复用计算单元,大大减少了硬件资源.在TSMC 90nm的工艺下,综合结果表明最高频率可以达到377 MHz,在搜索范围为±64时,能够达到超高清视频图像3 840×2 160@60f/s的实时处理速度.
【Abstract】 In this paper,a motion estimation algorithm suitable for hardware implementation is proposed for integer motion estimation,and the hardware architecture is also presented.By reusing computing unit in the CU depths,the hardware resource is greatly reduced.Synthesized results in the TSMC 90 nm show that the frequency of presented architecture can reach 377 MHz and the throughput can achieve 3 840×2 160@60f/s real-time processing in the search range of ±64,which meets the requirement of processing HD video images in real time.
【关键词】 视频编码;
HEVC;
运动估计;
硬件架构设计;
【Key words】 video coding; HEVC; motion estimation; hardware architecture design;
【Key words】 video coding; HEVC; motion estimation; hardware architecture design;
- 【文献出处】 微电子学与计算机 ,Microelectronics & Computer , 编辑部邮箱 ,2017年10期
- 【分类号】TN919.81
- 【被引频次】1
- 【下载频次】97