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PMOS管工艺参数对反相器SET效应的影响

Research of the Influence of PMOS Process Parameters on the Single Event Transient Effect

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【作者】 朱佳琪袁波吴秀龙

【Author】 ZHU Jiaqi;YUAN Bo;WU Xiulong;School of Electronics and Information Engineering,Anhui University;Sichuan Institute of Solid-State Circuits,China Electronics Technology Group Corp.;

【机构】 安徽大学电子信息工程学院中国电子科技集团公司第二十四研究所

【摘要】 研究了体硅CMOS工艺下数字集成电路的抗辐照特性。利用Synopsys公司的三维半导体器件模拟软件Sentaurus,对数字集成电路中的反相器电路进行单粒子瞬态(SET)效应仿真,分析PMOS管的各种工艺参数对反相器SET效应产生的脉冲电压的影响。研究结果表明,通过降低PMOS管的栅氧层厚度、n阱掺杂浓度、p+深阱掺杂浓度以及提高衬底浓度,可以有效地减小反相器SET脉冲电压的峰值和脉冲宽度。该研究结果对抗辐照数字集成电路设计具有一定的指导作用。

【Abstract】 Radiation hardened properties of digital integrated circuits in bulk CMOS process were investigated.Using the three-dimensional semiconductor device simulation software Sentaurus from Synopsys,the single event transient effect of a standard basic CMOS inverter cell was simulated.Changes in process parameters of PMOS could vary the pulse voltages generated by single event transient effect,which had been deeply studied.The results showed that the peak value and width of single pulse transient pulse voltage could be effectively reduced by decreasing the thickness of the gate oxide layer,the concentration of n-well doping and deep p+ doping,and by increasing the substrate doping.The results provided a reference for the designers engaged in the design of radiation hardened digital integrated circuits.

【基金】 国家自然科学基金资助项目(61674002)
  • 【分类号】TN432
  • 【被引频次】2
  • 【下载频次】107
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