【摘要】 基于Xilinx公司的Virtex-5系列FPGA开发板,采用VHDL硬件描述语言,并运用模块化的设计理念,参考TCP_IP协议栈的工作机制,设计并实现了一个具有接收确认及漏发重发功能的可靠的UDP_IP网络通信协议栈。同时,设计并实现了一个以太网控制器,该控制器与UDP_IP协议一起构成一个完整的网络通信链路协议。经过上板测试验证,该通信协议栈能正确高效地完成网络数据的发送和接收等工作,且稳定性良好。更多还原

【Abstract】 The paper design is based on Xilinx’s development board family of Virtex-5,and it uses hardware description language VHDL as the design language as well as using the concept of modular design,implemented a reliable UDP_IP network communication protocol stack with the function of receipt confirmation and retransmit the missed data which reference TCP_IP stack mechanism. At the same time,an Ethernet controller is designed and implemented,together with UDP_IP protocol,it forms a complete network communication link protocol. After download to the board,it has identified that the communication protocol stack can receive and transmit network data correctly,efficiently and stably.更多还原