【摘要】 卫星定位接收机中的卷积码译码即Viterbi译码,在处理器中面临着占有资源比较多、处理时间太长等问题,为了减少处理器中资源占用和提高它的处理速度,采用了多通道复用和串行加比选蝶形单元的方法,在FPGA平台上用硬件描述语言设计出一种高性能Viterbi译码器,大大减少资源占用,提高了接收机的处理速度。更多还原

【Abstract】 Satellite positioning receiver decoding convolutional code Viterbi decoder,facing the problem of share more resources and processing time in the processor,the processor in order to reduce the occupied resources and improve the processing speed,using multi channel multiplexing and serial plus selection butterfly unit method,using hardware description language to design a high performance Viterbi decoder FPGA platform,greatly reduce the resource utilization,improve the processing speed of the receiver.更多还原