【摘要】 为有效简化FPGA运算复杂度,降低FPGA处理时钟,在传统的滑动窗相关的基础上,结合1bit量化方法及多径能量积累的抗多径算法,提出了一种基于1bit量化的超宽带多路并行同步方法,在此基础上设计了FPGA实现方案.推导分析了1bit量化同步方法对系统性能的影响,给出了信噪比损失的量化结果.仿真结果表明,在低信噪比条件下,1bit量化方法引入2dB的信噪比损失.在高斯信道和瑞利信道下,通过针对虚警概率和漏检概率的分析及仿真,找到最优门限范围.更多还原

【Abstract】 In order to simplify the complexity and reduce clock of field programmable gate array(FPGA),an improved multi-channel parallel synchronization scheme was proposed based on traditional sliding window correlation,combining the 1bit quantification and multipath energy accumulation algorithm.In this paper,a method was designed to implement the FPGA,the influence of 1bit quantification on system performance was analyzed and the quantitative results of SNR loss was provided.The simulation results show that the 1bit quantification can bring 2dB SNR loss in Gaussian and Rayleigh channel.The best threshold range can be got through the simulation of false alarm probability and detection probability in Gaussian and Rayleigh channel.更多还原