节点文献
SHA-1算法的高速ASIC实现
The High-Throughput ASIC Implementation of SHA-1 Algorithm
【摘要】 SHA-1算法是一种国际标准的安全杂凑算法.为提高SHA-1算法的吞吐率,提出了一种新的五合一架构,该架构使SHA-1算法的迭代压缩由原来的80轮变为16轮,并可使每轮中某些f函数和部分加法移到关键路径外,从而缩短了关键路径,提高了吞吐率.在SMIC 65nm的工艺下,吞吐率达到12.68Gb/s,高于已发表的同类设计.
【Abstract】 SHA-1algorithm is one of the national standard for Secure Hash Algorithm.For the sake of accelerating the throughput of SHA-1algorithm,a new 5-in-1structure is proposed in this paper.This structure reduces the compression function from original 80 rounds to 16 5-in-1rounds and in each round some functions f and adders can be moved out of the critical path.Based on this,we can shorten the critical path and increase the throughput.In SMIC 65 nm technology,the throughput of SHA-1can achieve 12.68 Gb/s,which is higher than that of other reported designs and can meet the requirement of high throughput.This design also supports resuming transfer.
【Key words】 SHA-1 algorithm; high throughput; ASIC implementation; logical simplification;
- 【文献出处】 微电子学与计算机 ,Microelectronics & Computer , 编辑部邮箱 ,2016年10期
- 【分类号】TN918.1
- 【被引频次】3
- 【下载频次】113