【摘要】 由于SM4算法在CBC模式下存在从电路的输出端到输入端的反馈路径,所以流水线技术难以提高电路的吞吐率.针对这一问题,提出一种逻辑化简方法,使SM4加解密算法中每一个轮函数的关键路径减少1级异或门延时.基于这种方法,实现了一种4轮合1的SM4电路,在该电路的关键路径中可以减少4级异或门延时,且该电路与本文的其他方案相比有更高的单位面积吞吐率.ASIC实现的综合结果表明,4轮合1的SM4电路在CBC模式下的吞吐率达到5.24Gb/s,高于已发表的同类设计.更多还原

【Abstract】 In CBC mode,pipeline technique does not work on SM4 algorithm to increase throughput,as there is a feedback path from output to input.Over this problem,a logic simplifying method is proposed,which can reduce delay of one stage of XOR gates in each round function of encryption algorithm of SM4.Based on this method,SM4 with a 4-round-in-1structure is designed,in which,delay of 4stages of XOR gates can be reduced in the critical path,and this design has a higher throughput per unit area than the other schemes in this paper.Synthesis results show that the ASIC implementation of SM4 with a 4-round-in-1structure can achieve 5.24Gb/s in throughput,which is higher than that of reported designs.更多还原