【摘要】 基于SMIC 0.13μm CMOS工艺,设计了一种锁定频率范围为0.25~1.25GHz的低杂散锁相环频率合成器。该电路采用一种改进的高精度电荷泵,以减小电荷共享、电流失配等非理想效应,降低了相位误差,减少了输出信号的参考杂散;采用压控电阻器作为延迟单元,设计了一种输出频率广、相位噪声低的压控振荡器。Spectre仿真显示,输出电平在0.3~1.1V范围时,电荷泵的充放电电流失配仅为0.2%,锁相环锁定后的杂散小于-90dBm,满足了低杂散的设计要求。更多还原

【Abstract】 A low spurious phase locked loop(PLL)frequency synthesizer with a locking range of 0.25-1.25 GHz was designed in a SMIC 0.13μm CMOS process.A modified high precision charge pump was utilized to reduce the charge sharing,current mismatch and other non-ideal effects.So the phase offset and the reference spurs in the output signal were reduced.By using a voltage controlled resistor as the delay cell,a voltage controlled oscillator with wide tuning range and low phase noise was designed.Spectre simulation results showed that the charge pump achieved a charging/discharging current mismatch of only 0.2%in an output voltage range of 0.3-1.1V,and the whole PLL displayed a spur lower than-90 dBm at lock.It had met the requirements of low spur design.更多还原