【摘要】 针对边界扫描主控器常规实现方案执行速度慢,与通用处理器配合的专用边界扫描接口芯片仍然是依靠处理器运行边界扫描软件,测试速度不高,设计灵活性受到了接口芯片的限制的问题,提出了一种基于VHDL语言描述、FPGA实现的边界扫描主控器的硬件实现方法,设计了边界扫描主控器的基本结构,完成了主控器的VHDL模块化设计,并通过Quartus II开发平台,对各模块进行时序与功能仿真,实现了边界扫描主控器的单片集成。结果表明:用FPGA实现边界扫描主控器,时序验证方便,测试码加载速度快,修改灵活、系统集成度高,是实现边界扫描技术的一种新的有效思路。更多还原

【Abstract】 In the conventional implementation of the boundary scan master controller,the program implementation is slow,and the specialized interface chip matching with the general processor is still used by the processor to run boundary scan software,thus the test speed is not high and its design flexibility is limited by the interface chip.Based on VHDL language description,the hardware implementation method of boundary scan master controller realized by FPGA was proposed. The basic structure of the boundary scan master controller was designed,VHDL modular design of the main controller was completed,the timing and function of each module were simulated by using the Quartus II development platform,and a single chip integration of the boundary scan master controller is realized. The results showed that for the boundary scan master controller realized by using FPGA time sequence verification is convenient,loading speed in code testing is fast,modification is flexible and the system integration is high. It is a new effective way to realize the boundary scan technology.更多还原