【摘要】 介绍了一种常开型高压4H-SiC JFET的仿真与制造工艺。通过仿真对器件结构和加工工艺进行优化,指导下一步的工艺改进。在N+型4H-SiC衬底上生长掺杂浓度(ND)为1.0×1015 cm-3,厚度为50μm的N-外延层,并采用本实验室开发的SiC JFET工艺进行了器件工艺加工。通过测试,当栅极偏压VG=-6V时,研制的SiC JFET可以阻断3 000V电压;当栅极偏压VG=7V、漏极电压VD=3V时,正向漏极电流大于10A,对应的电流密度为100A/cm2。更多还原

【Abstract】 The simulation and manufacturing process of a high voltage normally-on 4H-SiC JFET were described in this paper.The simulation was conducted,in order to optimize device structure and the manufacturing process,and guide the following improvement of process.The devices were built on a 50μm thick and ND=1.0×1015 cm-3 doped n-type epilayer grown on N+4H-SiC.Its blocking voltage exceeds 3 000 Vat gate bias VG=-6Vand forward drain current exceeds 10 Aat gate bias VG=7Vand drain bias VD=3V,corresponding to the current density of 100A/cm2.更多还原