【摘要】 设计了一种基于FPGA快速进位链的时间-数字转换电路.该电路采用延迟内插技术,引入双链结构消除建立/保持时间对寄存器阵列输出结果的影响,并采用半周期平均延迟测试法,在Xilinx Virtex-4芯片上实测获得了59.19ps的分辨率.该电路采用使能控制模块将寄存器阵列输出结果的锁定时间控制在一个时钟周期内.使用FPGA Editor软件对该电路中单级延迟宏单元进行配置,并利用用户约束文件替代传统的手工布局布线,使得电路具有可移植性.此外,利用该电路对实测芯片中的CLB组合开关参数进行了测试,结果满足数据手册中提供的参数值的范围.更多还原

【Abstract】 A Time-to-Digital Converter(TDC)is implemented in a Field Programmable Gate Array(FPGA)using carry chains.The proposed architecture,based on the interpolation method,has double delay lines to eliminate the impact of setup time on the register array.It achieves 59.19 ps resolution with a self-test method presented by this paper.The dead time is limited within one period by an enable control module.This TDC is easy to implement in hardware with configured a macro delay cell and user constraints instead of manual place and route.Moreover,the combinational delays of CLB switching characteristics are tested using this TDC.更多还原