【摘要】 设计了一种应用于FPGA时钟管理的可变带宽锁相环.该锁相环采用开关电容滤波器实现可变电阻滤波功能,用反比N电流镜(N为反馈分频系数)来为电荷泵提供偏置,使电荷泵电流与偏置电路电流成1/N的比例关系.本文还提出了用虚拟开关减少了开关两端电压的非理想电荷效应,并设计了一种5级延时单元组成的环形压控振荡器,显著提升了输出频率范围.该锁相环实现了环路带宽与输入频率比值固定,从而使环路带宽能够自动跟随输入频率在较宽范围内变化,保证了其稳定性.本文采用CMOS 65nm数字工艺流片,电源电压为1.2V,作为时钟管理单元IP核嵌入于复旦大学自主研发的FDP5FPGA芯片中.测试表明,本文设计的PLL环路带宽在0.7MHz到13.4MHz能够跟随输入频率在18~252MHz范围内变化,输入频率与环路带宽比值近似为20,产生762MHz~1.7GHz的宽范围输出时钟,阻尼因子均方差不超过8%.更多还原

【Abstract】 A changeable bandwidth PLL is designed for FPGA’s clock management.Instead of using constant RC loop filter in fixed bandwidth PLL,this paper uses switched capacitor loop filter,to achieve changeable RC loop filter.It also uses inverse Ncurrent mirror to set the charge pump current to be 1/Nof the bias current.Thus the ratio of bandwidth and input frequency is fixed so that bandwidth can track input frequency in a wide range and maintains stable.This paper adopts a dummy switch structure in the switched capacitor loop filter to decrease the imperfect impact from the normal switch.A novel 5stage ring oscillator is designed to run at wide output frequency range.It is taped out in CMOS 65 nm technology,embedded as IP core in FDP5 FPGA,which is designed by Fudan University.The result suggests,the bandwidth of PLL can change from 0.7MHz to 13.4MHz,as the input frequency changes from 18 MHz to 252 MHz,the ratio of input frequency and bandwidth is kept about 20.The output frequency range of the PLL is 762 MHz to1.7GHz,RMS value of damping factor is less than 8%.更多还原