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DDS激励PLL高性能频率合成器设计

A High Performance Synthesizer Design Based on DDS Driving PLL

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【作者】 付钱华易淼

【Author】 FU Qianhua;YI Miao;School of Electrical Engineering and electronic Information,Xihua University;School of Information and Software Engineering,University of Electronic Science and Technology of China;College of Physics and Technology,Yichun University;

【机构】 西华大学电气与电子信息学院电子科技大学信息与软件工程学院宜春学院物理科学与工程技术学院

【摘要】 为适用CDMA各类收发机的射频本振的应用要求,研制了一种低杂散低相噪高分辨率的P波段频率合成器。利用DDS输出信号具有高分辨率和PLL具有窄带跟踪滤波特性,通过有效的频率规划和参数配置,规避了DDS由于相位截断近端杂散无法消除的缺陷,有效抑制了DDS中DAC非线性和幅度量化误差引起的宽带杂散。通过仿真分析了方案的可行性,设计了样品并进行了测试。结果显示,所设计的频率合成器输出频率范围为755 MHz~765 MHz,频率分辨率为100.5 k Hz,杂散优于-71 d Bc,相位噪声优于-105 d Bc/Hz@1 k Hz。

【Abstract】 A high resolution P-band synthesizer with low spurious and low phase noise was developed for fitting toall types of CDMA RF transceiver LO application requirements. The characteristic that DDS output signal has highresolution and PLL has narrowband tracking filter was full used,the defect of DDS was avoided,which narrow bandspurious are hardly eliminated,the wideband spurious of DDS that caused by DAC nonlinearity and amplitude quan-tization error are restrained effective,through frequency planning and parameters configuration. The feasibility ofscheme is analyzed by simulation,a synthesizer sample is developed and tested. The result shows its output frequen-cy range is 755 MHz~765 MHz,frequency resolution is 100.5 k Hz,spurious is better than-71 d Bc,phase noise isbetter than-105 d Bc/Hz@1 k Hz.

  • 【文献出处】 电子器件 ,Chinese Journal of Electron Devices , 编辑部邮箱 ,2016年01期
  • 【分类号】TN741
  • 【被引频次】11
  • 【下载频次】181
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