【摘要】 超标量处理器中的寄存器堆通常采用多端口结构以支持宽发射,这种结构对寄存器堆的速度、功耗和面积提出了很大的挑战。设计了一个64*64bit多端口寄存器堆,该寄存器堆能够在同一个时钟周期内完成8次读操作和4次写操作,通过对传统单端读写结构的存储单元进行改进,提出了电源门控与位线悬空技术相结合的单端读写结构的存储单元,12个读写端口全部采用传输门以加快访问速度。采用PTM 90nm、65nm、45nm和32nm仿真模型,在Hspice上进行仿真,与传统单端读写结构相比较,所提出的方法能够显著提升寄存器堆的性能,其中写1操作延时降低超过32%,总功耗降低超过45%,而且存储单元的稳定性也得到明显改善。更多还原

【Abstract】 Register files in superscalar processors usually adopt the multi-port structure to support the wide issue,however,this structure brings in problems such as prolonging access speed,increasing in silicon areas and higher power consumption.We design a 64*64bit multi-port register file which can concurrently accomplish 8read operations and 4write operations in one single clock cycle.We improve the conventional single-ended memory cell structure and purpose a new structure,which combines the power-gating and the bit-line floating techniques,and the transmission gate is used in all ports to accelerate the access speed.Simulations are conducted on Hspice with PTM 90 nm,65nm,45 nm and 32 nm technology models compared with the conventional single-ended structure,the proposed method can significantly improve the performance of register files,the delay of write logic 1decreases more than 32%,and the total power consumption decreases more than 45%;the stability of memory cells is also improved.更多还原