【摘要】 根据三重数据加密算法(3DES)的原理,采用全流水线和有限状态机,实现了基于现场可编程门阵列(FPGA)的3DES电路的仿真.基于Cyclone系列的EP3C40F780C6型FPGA芯片,采用自顶向下的设计思想进行电路的模块划分,有效的完成了3DES算法的总体结构和各个子模块的电路设计.利用超高速集成电路硬件描述语言(VHDL)完成了3DES加密算法的编写,并利用Altera公司的QuartusⅡ9.0综合工具对电路进行了仿真验证及逻辑综合.结果表明,该设计基本实现各模块的功能,获得了稳定的加密性能.更多还原

【Abstract】 According to the principle of the Triple Data Encryption Algorithm(3DES),we successfully design and simulation a 3DES circuit based on Field-Programmable Gate Array(FPGA).Based on the top-down design idea and the modularity of FPGA,we design an overall architecture of the 3DES encryption algorithm as well as the Circuit design of each sub-module,by using the EP3C40F780C6 FPGA chip of Cyclone series.We write and realize the computer programming of the 3DES encryption algorithm by employing the VHDL hardwire description language.And we perform the simulation and logic synthesis of the project using the Quartus Altera II 9.0synthesis tool(Altera Co.Ltd.).Comprehensive simulation results show that the basic function of each module has been achieved and the design meets with the desired results.更多还原