【摘要】 设计了一个应用于全数字锁相环的时间数字转换器(TDC).该时间数字转换器具有两种工作模式——粗量化和细量化.为了提高细量化模式的测量范围,TDC采用1-bit decision-select结构和游标门控环形振荡器(Vernier GRO)构成其两级量化单元.通过在Vernier GRO中使用一种新型结构的比较器,消除了用SR触发器做比较器时对测量范围的制约,也提高了GRO设计的灵活性.在TSMC 0.13μm工艺,1.2 V电源电压和40MHz采样速率下,仿真结果表明本设计的TDC在粗量化模式下具有不小于25ns的测量范围,在细量化模式下有效分辨率和测量范围分别为30ps,1.8ns.更多还原

【Abstract】 A Time-to-Digital Converter(TDC)for All-Digital Phase-Locked Loop(ADPLL)application is designed.The TDC has two operation modes,coarse mode and fine mode.To enlarge the detectable range of fine mode,the TDC utilizes 1-bit decision-select structure and Vernier GRO as its two-stage Quantization Unit.Using a new structure comparator in Vernier GRO eliminates the limitation to detectable range when using SR flip-flop as comparator,and also improve the design flexibility of GRO delay cell.The TDC is designed in TSMC 0.13μm CMOS technology.With 1.2Vpower supply and 40 MHz sampling rate,simulation result shows that detectable range of coarse mode can be 25 ns,effective resolution and detectable range of fine mode is 30 ps,1.8ns.更多还原