【摘要】 介绍了一种可重构直接射频采样接收机(RDRFR),而射频采样时钟抖动是影响RDRFR性能的主要因素之一。为了去采样时钟抖动,对射频采样时钟抖动进行了分析与建模,在此基础上研究了去采样时钟抖动的可行性方法。利用相位调制解调的思想,给出了去抖动电路的设计。在模拟噪声环境的基础上,对上述设计进行了仿真。仿真结果表明在皮秒级抖动下,去抖动后的信号频谱可恢复到理想无抖动信号的95.3%。所述方法达到了比较好的去抖动效果,验证了该方法的有效性。更多还原

【Abstract】 A reconfigurable direct RF receiver architecture( RDRFR) is presented,one of main factors which affects the performance of RDRFR is the sample clock jitter from the RDRFR. The sample clock jitter is analyzed and a model is built to mitigate sample clock jitter effects. Then the feasible method is disscussed to mitigate the sample clock jitter effects from the RDRFR on this basis. A module that is designed to reduce the jitter impacts is given by taking the advantage of phase modulation and demodulation. And then the module is simulated by imitating the environment of noise. The result shows that the signal after mitigating the sample clock jitter effects and the ideal signal is 95. 3 percent similar at the spectrum. The method described performs well and its validity is verified.更多还原