【摘要】 随着MOS制造工艺的不断发展,晶体管的特征尺寸越来越小,SRAM存储单元对制造工艺的要求也越来越高,功耗问题也越来越突出,该文设计的新型8管采用单个位线来进行读写操作,在两个交叉耦合的反相器之间加入PMOS晶体管来提高写能力。仿真的结果表明:与传统6管和7管相比,这种8管呈现出更好的读噪声容限、写裕度和保持存储数据的能力。更多还原

【Abstract】 As the CMOS process technology is continuingly developing, SRAM cell is more and more susceptive to increased pro-cess variation. The power consumption is becoming an important source. The proposed 8T SRAM cell uses a single-bit line struc-ture to perform read and write operation. The design improves the write ability by breaking-up the feedback loop of the inverterpair. The simulations show the proposed 8T cell offer better read static noise margin and write margin. Besides, the proposed cellhas a significant improvement in HSNM.更多还原