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On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS

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【作者】 任志雄; 张科峰; 刘览琦; 李聪; 陈晓飞; 刘冬生; 刘政林; 邹雪城;

【Author】 Ren Zhixiong;Zhang Kefeng;Liu Lanqi;Li Cong;Chen Xiaofei;Liu Dongsheng;Liu Zhenglin;Zou Xuecheng;School of Optical and Electronic Information,Huazhong University of Science and Technology;

【机构】 School of Optical and Electronic Information,Huazhong University of Science and Technology;

【摘要】 Three linear CMOS power amplifiers(PAs) with high output power(more than watt-level output power)for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer(PCT) and one 1.95 GHz PA using an on-chip series combining transformer(SCT) to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors(MGTR) and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC0.18 m RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 d B and 34.3 d B, a maximum output power of 30.7 d Bm and 29.4 d Bm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of37.5 d B, a maximum output power of 34.3 d Bm with 36.3% of peak PAE.

【Abstract】 Three linear CMOS power amplifiers(PAs) with high output power(more than watt-level output power)for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer(PCT) and one 1.95 GHz PA using an on-chip series combining transformer(SCT) to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors(MGTR) and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC0.18 m RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 d B and 34.3 d B, a maximum output power of 30.7 d Bm and 29.4 d Bm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of37.5 d B, a maximum output power of 34.3 d Bm with 36.3% of peak PAE.

【关键词】 CMOS; linearity; power combiner; transformers; power amplifier;
【Key words】 CMOS; linearity; power combiner; transformers; power amplifier;
【基金】 Project supported by the National Natural Science Foundation of China(No.61076030)
  • 【文献出处】 Journal of Semiconductors ,半导体学报(英文版) , 编辑部邮箱 ,2015年09期
  • 【分类号】TN722.75
  • 【被引频次】2
  • 【下载频次】47
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