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A capacitive DAC with custom 3-D 1-fF MOM unit capacitors optimized for fastsettling routing in high speed SAR ADCs

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【作者】 陈迟晓向济璇陈华斌许俊叶凡李宁任俊彦

【Author】 Chen Chixiao;Xiang Jixuan;Chen Huabin;Xu Jun;Ye Fan;Li Ning;Ren Junyan;State Key Laboratory of ASIC and System,Fudan University;

【机构】 State Key Laboratory of ASIC and System,Fudan University

【摘要】 Asynchronous successive approximation register(SAR) analog-to-digital converters(ADC) feature high energy efficiency but medium performance.From the point of view of speed,the key bottleneck is the unit capacitor size.In this paper,a small size three-dimensional(3-D) metal-oxide-metal(MOM) capacitor is proposed.The unit capacitor has a capacitance of 1-fF.It shapes as an umbrella,which is designed for fast settling consideration.A comparison among the proposed capacitor with other 3-D MOM capacitors is also given in the paper.To demonstrate the effectiveness of the MOM capacitor,a 6-b capacitive DAC is implemented in TSMC 1P9 M 65 nm LP CMOS technology.The DAC consumes a power dissipation of 0.16 mW at the rate of 100 MS/s,excluding a source-follower based output buffer.Static measurement result shows that INL is less than ± 1 LSB and DNL is less than ±0.5 LSB.In addition,a 100 MS/s 9-bit SAR ADC with the proposed 3-D capacitor is simulated.

【Abstract】 Asynchronous successive approximation register(SAR) analog-to-digital converters(ADC) feature high energy efficiency but medium performance.From the point of view of speed,the key bottleneck is the unit capacitor size.In this paper,a small size three-dimensional(3-D) metal-oxide-metal(MOM) capacitor is proposed.The unit capacitor has a capacitance of 1-fF.It shapes as an umbrella,which is designed for fast settling consideration.A comparison among the proposed capacitor with other 3-D MOM capacitors is also given in the paper.To demonstrate the effectiveness of the MOM capacitor,a 6-b capacitive DAC is implemented in TSMC 1P9 M 65 nm LP CMOS technology.The DAC consumes a power dissipation of 0.16 mW at the rate of 100 MS/s,excluding a source-follower based output buffer.Static measurement result shows that INL is less than ± 1 LSB and DNL is less than ±0.5 LSB.In addition,a 100 MS/s 9-bit SAR ADC with the proposed 3-D capacitor is simulated.

  • 【文献出处】 Journal of Semiconductors ,半导体学报(英文版) , 编辑部邮箱 ,2015年05期
  • 【分类号】TN792
  • 【被引频次】2
  • 【下载频次】56
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