【摘要】 设计通用的宏块并行的H.264帧内解码次序,避免了解码时的数据冲突,进而设计了存储器及计算单元可复用的帧内预测宏块并行解码单元,在解码速度提高的同时,尽量避免了资源的开销.通过对设计的并行解码器速度的测试及DC综合的结果,验证了设计的可复用的宏块并行帧内解码器的VLSI结构有效性,每个宏块解码平均速度到达了113cycles.更多还原

【Abstract】 This paper presents a VLSI architecture design of macroblock-parallel intraframe decoder to avoid the data conflicts,providing guarantee for decdoding correctness.The memory reuse,calculation unit reuse and macroblockparallel intra prediction module is designed which can improve the decoding speed and increase the utilization of resources at the same time.The functional testing and DC analysis has demonstrated the proposed macroblockparallel VLSI architecture of intra decoder.It achieves a decoding speed at 113cycles/MB.更多还原